B1.15 CCSIDR, Cache Size ID Register

The CCSIDR provides information about the architecture of the currently selected cache.

Bit field descriptions

CCSIDR is a 32-bit register and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-11 CCSIDR bit assignments
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WT, [31]

Indicates whether the selected cache level supports Write-Through:

0

Cache Write-Through is not supported at any level.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

WB, [30]

Indicates whether the selected cache level supports Write-Back. Permitted values are:

0

Write-Back is not supported.

1

Write-Back is supported.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

RA, [29]

Indicates whether the selected cache level supports read-allocation. Permitted values are:

0

Read-allocation is not supported.

1

Read-allocation is supported.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

WA, [28]

Indicates whether the selected cache level supports write-allocation. Permitted values are:

0

Write-allocation is not supported.

1

Write-allocation is supported.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

NumSets, [27:13]

(Number of sets in cache) - 1. Therefore, a value of 0 indicates one set in the cache. The number of sets does not have to be a power of 2.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

Associativity, [12:3]

(Associativity of cache) - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

LineSize, [2:0]

(Log2(Number of bytes in cache line)) - 4. For example:

Indicates the (log2 (number of words in cache line)) - 2:

For a line length of 16 bytes: Log2(16) = 4, LineSize entry = 0. This is the minimum line length.

For a line length of 32 bytes: Log2(32) = 5, LineSize entry = 1.

For more information about encoding, see Table   B1-6 CCSIDR encodings.

Configurations

CCSIDR is architecturally mapped to AArch64 register CCSIDR_EL1. See B2.23 CCSIDR_EL1, Cache Size ID Register, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

The implementation includes one CCSIDR for each cache that it can access. CSSELR selects which Cache Size ID Register is accessible.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

CCSIDR encodings

The following table shows the individual bit field and complete register encodings for the CCSIDR. The CSSELR determines which CCSIDR to select.

Table B1-6 CCSIDR encodings

CSSELR Cache Size Complete register encoding Register bit field encoding
Level InD WT WB RA WA NumSets Associativity LineSize
0b000 0b0 L1 Data cache 16KB 7007E01A 0 1 1 1 003F 003 2
32KB 700FE01A 007F 003 2
64KB 701FE01A 00FF 003 2
0b000 0b1 L1 Instruction cache 16KB 2007E01A 0 0 1 0 003F 003 2
32KB 200FE01A 007F 003 2
64KB 201FE01A 00FF 003 2
0b001 0b0 L2 cache Not present See following Note. - - - - - - -
64KB 701FE01A 0 1 1 1 00FF 003 2
128KB 703FE01A 01FF 003 2
256KB 707FE01A 03FF 003 2
0b001 0b1 Reserved - - - - - - - - -
0b010 0b0 L3 cache 256KB 701FE07A 0 1 1 1 000F 00F 2
512KB 703FE07A 01FF 00F 2
1MB 707FE07A 03FF 00F 2
2MB 70FFE07A 07FF 00F 2
4MB 71FFE07A 0FFF 00F 2
8MB 73FFE07A 1FFF 00F 2
0b0101 - 0b1111 Reserved - - - - - - - - -

Note:

If no L2 cache is present the core uses L3 cache as L2, and the L3 encodings apply.
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