B1.16 CLIDR, Cache Level ID Register

The CLIDR identifies the type of cache, or caches, implemented at each level, up to a maximum of seven levels.

It also identifies the Level of Coherency (LoC) and Level of Unification (LoU) for the cache hierarchy.

Bit field descriptions

CLIDR is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-12 CLIDR bit assignments
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ICB, [31:30]

Inner cache boundary. This field indicates the boundary between the inner and the outer domain:

0b10L2 cache is the highest inner level.
0b11L3 cache is the highest inner level.
LoUU, [29:27]

Indicates the Level of Unification Uniprocessor for the cache hierarchy:

0b0000 No levels of cache need to cleaned or invalidated when cleaning or invalidating to the Point of Unification. This is the value if no cache are configured.
LoC, [26:24]

Indicates the Level of Coherency for the cache hierarchy:

0b010L3 cache is not implemented.
0b011L2 and L3 cache are implemented.
LoUIS, [23:21]

Indicates the Level of Unification Inner Shareable (LoUIS) for the cache hierarchy.

0b000No levels of cache need to cleaned or invalidated when cleaning or invalidating to the Point of Unification.
RES0, [20:9]

No cache at levels L7 down to L4.

RES0Reserved.
Ctype3, [8:6]

Indicates the type of cache if the cluster implements L3 cache. If present, unified instruction and data caches at Level-3:

0b000L3 cache is not implemented.
0b100L3 cache is implemented.

If Ctype2 has a value of 0b000, the value of Ctype3 must be ignored.

Ctype2, [5:3]

Indicates the type of cache if the core implements L2 cache. If present, unified instruction and data caches at Level-2:

0b100L2 cache is implemented as a unified cache.
Ctype1, [2:0]

Indicates the type of cache implemented at L1:

0b011Separate instruction and data caches at L1.
Configurations

CLIDR is architecturally mapped to AArch64 register CLIDR_EL1. See B2.24 CLIDR_EL1, Cache Level ID Register, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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