B1.17 CPACR, Architectural Feature Access Control Register

The CPACR controls access to floating-point, and Advanced SIMD functionality from EL0, EL1, and EL3.

Bit field descriptions

CPACR is a 32-bit register, and is part of the Other system control registers functional group.

Figure B1-13 CPACR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


TRCDIS, [28]
This bit is reserved, RES0.
Configurations

CPACR is architecturally mapped to AArch64 register CPACR_EL1. See B2.25 CPACR_EL1, Architectural Feature Access Control Register, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Bits in the NSACR control Non-secure access to the CPACR fields. See the field descriptions cp10 and cp11.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.