B1.20 CPUECTLR, CPU Extended Control Register

The CPUECTLR provides extra IMPLEMENTATION DEFINED configuration and control options for the core.

Bit field descriptions

CPUECTLR is a 64-bit register, and is part of the 64-bit registers functional group.

Figure B1-16 CPUECTLR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [63:40]
RES0Reserved.
ATOM, [39:38]
00

Atomic instructions are performed near if they hit in the cache in a unique state, or far if they miss or are shared. For more details, see A6.4.1 Memory system implementation. This is the default.

01

Force all cacheable atomic instructions to be executed near, in the L1 cache.

10

Force most cacheable atomic instructions to be executed far, in the L3 cache or beyond.

11

Force cacheable load atomics, including SWP and CAS, to be executed near, in the L1 cache. Store atomics are performed near if they hit in the cache in a unique state, or far if they miss or are shared.

L2FLUSH, [37]
0

L2 cache flushes, for example during a core powerdown sequence, cause clean lines to be allocated into the L3 cache rather than discarding them. This can improve performance if it is known that the data is likely to be used soon by another core.

1

Clean lines do not provide data when being evicted during a cache flush and do not allocate to the L3 cache. If the line is being evicted from the cluster, the DSU will generate evict transactions to update the interconnect snoop filter depending on the DSU programming.

RES0, [36:31]
RES0Reserved.
L3WSCTL, [30:29]

Write streaming no-L3-allocate threshold. The possible values are:

00

128th consecutive streaming cache line does not allocate in the L1, L2, or L3 cache.

01

1024th consecutive streaming cache line does not allocate in the L1, L2, or L3 cache. This is the reset value.

10

4096th consecutive streaming cache line does not allocate in the L1, L2, or L3 cache.

11

Disables streaming. All write-allocate lines allocate in the L1, L2, or L3 cache.

L2WSCTL, [28:27]

Write streaming no-L2-allocate threshold. The possible values are:

00

16th consecutive streaming cache line does not allocate in the L1 or L2 cache.

01

128th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is the reset value.

10

512th consecutive streaming cache line does not allocate in the L1 or L2 cache.

11

Disables streaming. All write-allocate lines allocate in the L1 or L2 cache.

L1WSCTL, [26:25]

Write streaming no-L1-allocate threshold. The possible values are:

00

4th consecutive streaming cache line does not allocate in the L1 cache. This is the reset value.

01

64th consecutive streaming cache line does not allocate in the L1 cache.

10

128th consecutive streaming cache line does not allocate in the L1

11

Disables streaming. All write-allocate lines allocate in the L1 cache.

RES0, [24:16]
RES0Reserved.
L1PCTL, [15:13]

L1 Data prefetch control. The value of the L1PCTL field determines the maximum number of outstanding data prefetches allowed in the L1 memory system (not counting the data prefetches generated by software load/PLD instructions).

000

Prefetch disabled.

001

1 outstanding prefetch allowed.

010

2 outstanding prefetches allowed.

011

3 outstanding prefetches allowed.

100

4 outstanding prefetches allowed.

101

5 outstanding prefetches allowed. This is the reset value.

110

6 outstanding prefetches allowed.

111

7 outstanding prefetches allowed.

L3PCTL, [12:10]

L3 Data prefetch control. The value of the L3PCTL field determines the approximate distance between the L1 prefetcher and requests sent to the L3 memory system. Increasing this distance may improve performance on systems with higher latency to main memory, but increasing it too far can reduce performance.

Note:

The L3 memory system may have more outstanding access to the system than this number.
000

Fetch 16 lines ahead.

001

Fetch 32 lines ahead.

010

Reserved.

011

Reserved.

100

Disable L3 prefetching.

101

Fetch 2 lines ahead.

110

Fetch 4 lines ahead.

111

Fetch 8 lines ahead. This is the reset value.

RES0, [9:1]
RES0Reserved.
EXTLLC, [0]
0

Indicates that the L3 cache is the external Last-level cache in the system. This is the reset value.

1

Indicates that an external Last-level cache is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count.

Configurations

The CPUECTLR is mapped to the AArch64 CPUECTLR_EL1 register. See B2.30 CPUECTLR_EL1, CPU Extended Control Register, EL1.

Usage constraints

Accessing the CPUECTLR

The CPUECTLR can be written dynamically.

This register can be read using MRRC with the following syntax:

MRRC <syntax>

This register can be written using MRRC with the following syntax:

MCRR <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<syntax> coproc opc1 CRm
p15, 4, <Rt>, <Rt2>, c15 1111 0100 1111
Accessibility

This register is accessible in software as follows:

<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
p15, 1, <Rt>, <Rt2>, c15 x x 0 - RW n/a RW
p15, 1, <Rt>, <Rt2>, c15 x 0 1 - RW RW RW
p15, 1, <Rt>, <Rt2>, c15 x 1 1 - n/a RW RW

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.