B1.26 CSSELR, Cache Size Selection Register

The CSSELR selects the current CCSIDR by specifying:

  • The required cache level.
  • The cache type, either instruction or data cache.

For details of the CCSIDR, see B1.15 CCSIDR, Cache Size ID Register.

Bit field descriptions

CSSELR is a 32-bit register, and is part of the Identification registers functional group.

Figure B1-22 CSSELR bit assignments
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RES0, [31:4]
RES0Reserved.
Level, [3:1]

Cache level of required cache:

0b000L1.
0b001

L2.

Only if L2 is present, or if no L2 present then L3 is present.

0b010L3. Only if L3 exists.

The combination of Level=0b001 and InD=0b1 is reserved.

The combinations of Level and InD for 0b0100 to 0b1111 are reserved.

InD, [0]

Instruction not Data bit:

0b0Data or unified cache.
0b1Instruction cache.

The combination of Level=0b001 or Level=0b010 and InD=0b1 is reserved.

The combinations of Level and InD for 0b0100 to 0b1111 are reserved.

Configurations

CSSELR (NS) is architecturally mapped to AArch64 register CSSELR_EL1. See B2.36 CSSELR_EL1, Cache Size Selection Register, EL1.

If a cache level is missing but CSSELR selects this level, then CCSIDR is L1 cache as CSSERL is RES0 for all bits when programmed with a cache level which does not exist.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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