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The CTR provides information about the architecture of the caches.
CTR is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Cache Write-Back granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:
|Cache Write-Back granule size is 16 words.|
Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:
|Exclusive reservation granule size is 16 words.|
Log2 of the number of words in the smallest cache line of all the data and unified caches that the core controls:
|Smallest data cache line size is 16 words.|
Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
|Virtually Indexed Physically Tagged (VIPT).|
Log2 of the number of words in the smallest cache line of all the instruction caches that the core controls.
|Smallest instruction cache line size is 16 words.|
CTR is architecturally mapped to AArch64 register CTR_EL0. See B2.37 CTR_EL0, Cache Type Register, EL0.
There is one copy of this register that is used in both Secure and Non-secure states.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.