B1.47 HACR, Hyp Auxiliary Configuration Register

HACR controls trapping to Hyp mode of implementation defined aspects of Non-secure EL1 or EL0 operation. This register is not used in the Cortex®-A55 core.

Bit field descriptions

HACR is a 32-bit register, and is part of the Virtualization registers functional group.

Figure B1-32 HACR bit assignments
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RES0, [31:0]

AArch32 System register HACR is architecturally mapped to AArch64 System register HACR_EL2. See B2.54 HACR_EL2, Hyp Auxiliary Configuration Register, EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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