B1.54 HCR, Hyp Configuration Register

The HCR provides configuration controls for virtualization, including defining whether various Non-secure operations are trapped to Hyp mode.

Bit field descriptions

HCR is a 32-bit register, and is part of the Virtualization registers functional group.

This register resets to value 0x00000002.

Figure B1-39 HCR bit assignments
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RES0, [31]
RES0, [29:28]
TGE, [27]

Trap General Exceptions. If this bit is set, and SCR_EL3.NS is set, then:

All exceptions that would be routed to EL1 are routed to EL2.

  • The SCTLR.M bit is treated as 0 regardless of its actual state, other than for reading the bit.
  • The HCR.FMO, IMO, and AMO bits are treated as 1 regardless of their actual state, other than for reading the bits.
  • All virtual interrupts are disabled.
  • An exception return to EL1 is treated as an illegal exception return.

The Cortex®-A55 core does not support any implementation defined mechanisms for signaling virtual interrupts.

Additionally, if HCR.TGE is 1, the HDCR.{TDRA,TDOSA,TDA} bits are ignored and the core behaves as if they are set to 1, other than for the value read back from HDCR.

TSC, [19]

Trap SMC instruction. When this bit is set to 1, any attempt from a Non-secure EL1 state to execute an SMC instruction, that passes its condition check if it is conditional, is trapped to Hyp mode.

SWIO, [1]

Set/Way Invalidation Override. This bit is RES1.


HCR is architecturally mapped to AArch64 register HCR_EL2[31:0]. See B2.55 HCR_EL2, Hypervisor Configuration Register, EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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