B1.55 HCR2, Hyp Configuration Register 2

The HCR2 provides additional configuration controls for virtualization.

Bit field descriptions

HCR2 is a 32-bit register, and is part of the Virtualization registers functional group.

This register resets to value 0x00000000.

Figure B1-40 HCR2 bit assignments
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MIOCNCE, [6]

Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure PL1&0 translation regime.

This bit is not implemented, RAZ/WI.

Configurations

HCR2 is architecturally mapped to AArch64 register HCR_EL2[63:32]. See B2.55 HCR_EL2, Hypervisor Configuration Register, EL2.

This register is accessible only at EL2 or EL3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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