B1.56 HSCTLR, Hyp System Control Register

The HSCTLR provides top level control of the system operation in Hyp mode.

This register provides Hyp mode control of features controlled by the Banked SCTLR bits, and shows the values of the non-Banked SCTLR bits.

Bit field descriptions

HSCTLR is a 32-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Other system control registers functional group.
Figure B1-41 HSCTLR bit assignments
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I, [12]

Instruction cache enable. This is an enable bit for instruction caches at EL2:

0Instruction caches disabled at EL2. If HSCTLR.M is set to 0, instruction accesses from stage 1 of the EL2 translation regime are to Normal memory, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable. This is the reset value.
1Instruction caches enabled at EL2. If HSCTLR.M is set to 0, instruction accesses from stage 1 of the EL2 translation regime are to Normal memory, Outer Shareable, Inner Write-Through, Outer Write-Through.

When this bit is 0, all EL2 Normal memory instruction accesses are Non-cacheable.

The reset value for this field is unknown.

C, [2]

Cache enable. This is an enable bit for data and unified caches at EL2:

0Data and unified caches disabled at EL2. This is the reset value.
1Data and unified caches enabled at EL2.

When this bit is 0, all EL2 Normal memory data accesses and all accesses to the EL2 translation tables are Non-cacheable.

The reset value for this field is unknown.

M, [0]

MMU enable. This is a global enable bit for the EL2 stage 1 MMU:

0EL2 stage 1 MMU disabled. This is the reset value.
1EL2 stage 1 MMU enabled.

The reset value for this field is unknown.

Configurations

HSCTLR is architecturally mapped to AArch64 register SCTLR_EL2. See B2.95 SCTLR_EL2, System Control Register, EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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