B1.57 HSR, Hyp Syndrome Register

The HSR holds syndrome information for an exception taken to Hyp mode.

Bit field descriptions

HSR is a 32-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Exception and fault handling registers functional group.
Figure B1-42 HSR bit assignments
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EC, [31:26]

Exception class. The exception class for the exception that is taken in Hyp mode. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

IL, [25]

Instruction length. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

ISS, [24:0]

Instruction specific syndrome. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information. The interpretation of this field depends on the value of the EC field. See B1.57.1 Encoding of ISS[24:20] when HSR[31:30] is 0b00.

Configurations

HSR is architecturally mapped to AArch64 register ESR_EL2. See B2.52 ESR_EL2, Exception Syndrome Register, EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsection:
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