|Home > Register Descriptions > AArch32 system registers > ID_AFR0, Auxiliary Feature Register 0|
The ID_AFR0 provides information about the implementation defined features of the PE in AArch32. This register is not used in the Cortex®-A55 core.
ID_AFR0 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
AArch32 System register ID_AFR0 is architecturally mapped to AArch64 System register ID_AFR0_EL1. See B2.65 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.