B1.60 ID_DFR0, Debug Feature Register 0

The ID_DFR0 provides top-level information about the debug system in AArch32.

Bit field descriptions

ID_DFR0 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-45 ID_DFR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:28]
res0Reserved.
PerfMon, [27:24]

Indicates support for performance monitor model:

0x4Support for Performance Monitor Unit version 3 (PMUv3) system registers, with a 16-bit evtCount field.
MProfDbg, [23:20]

Indicates support for memory-mapped debug model for M profile cores:

0x0This product does not support M profile Debug architecture.
MMapTrc, [19:16]

Indicates support for memory-mapped trace model:

0x1Support for Arm trace architecture, with memory-mapped access.

In the Trace registers, the ETMIDR gives more information about the implementation.

CopTrc, [15:12]

Indicates support for coprocessor-based trace model:

0x0This product does not support Arm trace architecture.
RES0, [11:8]
res0Reserved.
CopSDbg, [7:4]

Indicates support for coprocessor-based Secure debug model:

0x8This product supports v8.2 Debug architecture.
CopDbg, [3:0]

Indicates support for coprocessor-based debug model:

0x8This product supports v8.2 Debug architecture.
Configurations

ID_DFR0 is architecturally mapped to AArch64 register ID_DFR0_EL1. See B2.66 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.