B1.63 ID_ISAR2, Instruction Set Attribute Register 2

The ID_ISAR2 provides information about the instruction sets implemented by the core in AArch32.

Bit field descriptions

ID_ISAR2 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-48 ID_ISAR2 bit assignments
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Reversal, [31:28]

Indicates the implemented Reversal instructions:

0x2
  • The REV, REV16, and REVSH instructions.
  • The RBIT instruction.
PSR_AR, [27:24]

Indicates the implemented A and R profile instructions to manipulate the PSR:

0x1The MRS and MSR instructions, and the exception return forms of data-processing instructions.

The exception return forms of the data-processing instructions are:

  • In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit set.
  • In the T32 instruction set, the SUBS PC, LR, #N instruction.
MultU, [23:20]

Indicates the implemented advanced unsigned Multiply instructions:

0x2
  • The UMULL and UMLAL instructions.
  • The UMAAL instruction.
MultS, [19:16]

Indicates the implemented advanced signed Multiply instructions.

0x3
  • The SMULL and SMLAL instructions.
  • The SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions, and the Q bit in the PSRs.
  • The SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.
Mult, [15:12]

Indicates the implemented additional Multiply instructions:

0x2
  • The MUL instruction.
  • The MLA instruction.
  • The MLS instruction.
MultiAccessInt, [11:8]

Indicates the support for interruptible multi-access instructions:

0x0No support. This means that the LDM and STM instructions are not interruptible.
MemHint, [7:4]

Indicates the implemented memory hint instructions:

0x4
  • The PLD instruction.
  • The PLI instruction.
  • The PLDW instruction.
LoadStore, [3:0]

Indicates the implemented additional load/store instructions:

0x2
  • The LDRD and STRD instructions.
  • The Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, and LDAEXD) and Store Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, and STLEXD) instructions.
Configurations

ID_ISAR2 is architecturally mapped to AArch64 register ID_ISAR2_EL1. See B2.69 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See:

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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