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The ID_ISAR3 provides information about the instruction sets implemented by the core in AArch32.
ID_ISAR3 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Indicates the implemented Thumb Execution Environment (T32EE) instructions:
Indicates the implemented true NOP instructions:
Indicates the support for T32 non flag-setting
|Support for T32 instruction set encoding T1 of the
Indicates the implemented Table Branch instructions in the T32 instruction set.
Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions.
Indicates the implemented SVC instructions:
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
||The SIMD field relates only to implemented instructions that perform SIMD operations on the general-purpose registers. In an implementation that supports Advanced SIMD and floating-point instructions, MVFR0, MVFR1, and MVFR2 give information about the implemented Advanced SIMD instructions.|
Indicates the implemented Saturate instructions:
ID_ISAR3 is architecturally mapped to AArch64 register ID_ISAR3_EL1. See B2.70 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR4, and ID_ISAR5. See:
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.