B1.66 ID_ISAR5, Instruction Set Attribute Register 5

The ID_ISAR5 provides information about the instruction sets that the core implements.

Bit field descriptions

ID_ISAR5 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-51 ID_ISAR5 bit assignments
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RES0, [31:28]
res0Reserved.
RDM, [27:24]

VQRDMLAH and VQRDMLSH instructions in AArch32. The value is:

0x1VQRDMLAH and VQRDMLSH instructions are implemented.
RES0, [23:20]
res0Reserved.
CRC32, [19:16]

Indicates whether CRC32 instructions are implemented in AArch32 state. The value is:

0x1CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW instructions are implemented.
SHA2, [15:12]

Indicates whether SHA2 instructions are implemented in AArch32 state:

0x0No SHA2 instructions implemented. This is the value when the Cryptographic Extensions are not implemented or are disabled.
0x1SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 implemented. This is the value when the Cryptographic Extensions are implemented and enabled.
SHA1, [11:8]

Indicates whether SHA1 instructions are implemented in AArch32 state. Defined values are:

0x0No SHA1 instructions implemented. This is the value when the Cryptographic Extensions are not implemented or are disabled.
0x1SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 implemented. This is the value when the Cryptographic Extensions are implemented and enabled.
AES, [7:4]

Indicates whether AES instructions are implemented in AArch32 state. Defined values are:

0x0No AES instructions implemented. This is the value when the Cryptographic Extensions are not implemented or are disabled.
0x2
  • AESE, AESD, AESMC, and AESIMC implemented.
  • PMULL/PMULL2 instructions operating on 64-bit data quantities.

This is the value when the Cryptographic Extensions are implemented and enabled.

SEVL, [3:0]

Indicates whether the SEVL instruction is implemented in AArch32. The value is:

0x1SEVL is implemented as send event local.
Configurations

ID_ISAR5 is architecturally mapped to AArch64 register ID_ISAR5_EL1. See B2.72 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

ID_ISAR5 must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR4. See:

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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