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The ID_MMFR2 provides information about the implemented memory model and memory management support in AArch32.
ID_MMFR2 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Hardware Access Flag. Indicates support for a Hardware Access flag, as part of the VMSAv7 implementation:
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
|Support for WFI stalling.|
Memory Barrier. Indicates the supported CP15 memory barrier operations.
Supported CP15 memory barrier operations are:
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.
Supported unified TLB maintenance operations are:
Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB implementation:
L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a Harvard cache implementation:
L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch operations, for a Harvard cache implementation:
L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch operations, for a Harvard cache implementation:
ID_MMFR2 is architecturally mapped to AArch64 register ID_MMFR2_EL1. See B2.76 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
Must be interpreted with ID_MMFR0, ID_MMFR1, ID_MMFR3, and ID_MMFR4. See:
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.