B1.71 ID_MMFR3, Memory Model Feature Register 3

The ID_MMFR3 provides information about the memory model and memory management support in AArch32.

Bit field descriptions

ID_MMFR3 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-56 ID_MMFR3 bit assignments
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Supersec, [31:28]

Supersections. Indicates support for supersections:

0x0Supersections supported.
CMemSz, [27:24]

Cached Memory Size. Indicates the size of physical memory supported by the core caches:

0x21TByte, corresponding to a 40-bit physical address range.
CohWalk, [23:20]

Coherent walk. Indicates whether translation table updates require a clean to the point of unification:

0x1Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.
PAN, [19:16]

Privileged Access Never. Indicates support for the PAN bit in CPSR, SPSR, and DSPSR in AArch32.

0x2
  • PAN supported.
  • ATS1CPRP and ATS1CPWP supported.
MaintBcst, [15:12]

Maintenance broadcast. Indicates whether cache, TLB, and branch predictor operations are broadcast:

0x2Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions.
BPMaint, [11:8]

Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.

0x2

Supported branch predictor maintenance operations are:

  • Invalidate all branch predictors.
  • Invalidate branch predictors by Virtual Address (VA).
CMaintSW, [7:4]

Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.

0x1

Supported hierarchical cache maintenance operations by set/way are:

  • Invalidate data cache by set/way.
  • Clean data cache by set/way.
  • Clean and invalidate data cache by set/way.
CMaintVA, [3:0]

Cache maintenance by VA. Indicates the supported cache maintenance operations by VA.

0x1

Supported hierarchical cache maintenance operations by VA are:

  • Invalidate data cache by VA.
  • Clean data cache by VA.
  • Clean and invalidate data cache by VA.
  • Invalidate instruction cache by VA.
  • Invalidate all instruction cache entries.
Configurations

ID_MMFR3 is architecturally mapped to AArch64 register ID_MMFR3_EL1. See B2.77 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Must be interpreted with ID_MMFR0, ID_MMFR1, ID_MMFR2, and ID_MMFR4. See:

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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