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The ID_MMFR3 provides information about the memory model and memory management support in AArch32.
ID_MMFR3 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Supersections. Indicates support for supersections:
Cached Memory Size. Indicates the size of physical memory supported by the core caches:
|1TByte, corresponding to a 40-bit physical address range.|
Coherent walk. Indicates whether translation table updates require a clean to the point of unification:
|Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.|
Privileged Access Never. Indicates support for the PAN bit in CPSR, SPSR, and DSPSR in AArch32.
Maintenance broadcast. Indicates whether cache, TLB, and branch predictor operations are broadcast:
|Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions.|
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
Supported branch predictor maintenance operations are:
Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.
Supported hierarchical cache maintenance operations by set/way are:
Cache maintenance by VA. Indicates the supported cache maintenance operations by VA.
Supported hierarchical cache maintenance operations by VA are:
ID_MMFR3 is architecturally mapped to AArch64 register ID_MMFR3_EL1. See B2.77 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
Must be interpreted with ID_MMFR0, ID_MMFR1, ID_MMFR2, and ID_MMFR4. See:
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.