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The ID_PFR0 provides top-level information about the instruction sets supported by the core in AArch32.
ID_PFR0 is a 32-bit register, and must be interpreted with ID_PFR1. It is part of the Identification registers functional group.
This register is Read Only.
RAS extension version. The value is:
|Version 1 of the RAS extension is present.|
Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
|Core does not support the T32EE instruction set.|
Indicates support for Jazelle. This value is:
|Core supports trivial implementation of Jazelle.|
Indicates support for T32 instruction set. This value is:
|Core supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit T32 basic instructions.|
Indicates support for A32 instruction set. This value is:
|A32 instruction set implemented.|
ID_PFR0 is architecturally mapped to AArch64 register ID_PFR0_EL1. See B2.79 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.