B1.74 ID_PFR1, Processor Feature Register 1

The ID_PFR1 provides information about the programmers model and architecture extensions supported by the core.

Bit field descriptions

ID_PFR1 is a 32-bit register, and must be interpreted with ID_PFR0. It is part of the Identification registers functional group.

This register is Read Only.

Figure B1-59 ID_PFR1 bit assignments
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GIC CPU, [31:28]

GIC CPU support:

0x0GIC CPU interface is disabled, GICCDISABLE is HIGH.
0x1GIC CPU interface is enabled, GICCDISABLE is LOW.
RES0, [27:20]
GenTimer, [19:16]

Generic Timer support:

0x1Generic Timer is implemented.
Virtualization, [15:12]

Indicates support for Virtualization:

0x1The following Virtualization is implemented:
  • The SCR.SIF bit.
  • The modifications to the SCR.AW and SCR.FW bits described in the Virtualization Extensions.
  • The MSR (Banked register) and MRS (Banked register) instructions.
  • The ERET instruction.
  • EL2, Hyp mode, the HVC instruction implemented.
MProgMod, [11:8]

M profile programmers model support:

0x0Not supported.
Security, [7:4]

Security support:

0x1The following Security items are implemented:
  • The VBAR register.
  • The TTBCR.PD0 and TTBCR.PD1 bits.
  • The ability to access Secure or Non-secure physical memory is supported.
  • EL3, Monitor mode, the SMC instruction implemented.
ProgMod, [3:0]

Indicates support for the standard programmers model for Armv4 and later.

Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:


ID_PFR1 is architecturally mapped to AArch64 register ID_PFR1_EL1. See B2.80 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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