B1.75 IFSR, Instruction Fault Status Register

The IFSR holds status information about the last instruction fault.

Bit field descriptions

IFSR is a 32-bit register, and is part of the Exception and fault handling registers functional group.

There are two formats for this register. The current translation table format determines which format of the register is used.

Configurations

IFSR (NS) is architecturally mapped to AArch64 register IFSR32_EL2. See B2.82 IFSR32_EL2, Instruction Fault Status Register, EL2.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.