B1.78 PAR, Physical Address Register

The PAR returns the output address (OA) from an address translation instruction that executed successfully, or fault information if the instruction did not execute successfully.

Configuration Details

PAR is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, accesses read and write bits[31:0] and do not modify bits[63:32].

PAR is part of the Address translation instructions functional group.


AArch32 System register PAR is architecturally mapped to AArch64 System register PAR_EL1. See B2.91 PAR_EL1, Physical Address Register, EL1.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.