B1.81 SCTLR, System Control Register

The SCTLR provides the top-level control of the system, including its memory system.

Bit field descriptions

SCTLR is a 32-bit register, and is part of the Other system control registers functional group.

Figure B1-70 SCTLR bit assignments
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TE, [30]

T32 Exception enable.

This field resets to a value determined by the input configuration signal cfgte_i.

AFE, [29]

Access Flag Enable.

This field resets to 0.

TRE, [28]

TEX remap enable.

This field resets to 0.

EE, [25]

Exception Endianness bit.

This field resets to a value determined by the input configuration signal cfgend_i.

SPAN, [23]

This field resets to 1.

UWXN, [20]

Unprivileged write permission implies PL1 XN (Execute-never).

This field resets to 0.

WXN, [19]

Write permission implies XN (Execute-never).

This field resets to 0.

nTWE, [18]

Traps PL0 execution of WFE instructions to Undefined mode.

This field resets to 1.

nTWI, [16]

Traps PL0 execution of WFI instructions to Undefined mode.

This field resets to 1.

V, [13]

Vectors bit.

This field resets to a value determined by the input configuration signal vinithi_i.

I, [12]

Instruction access Cacheability control, for accesses at EL1 and EL0.

This field resets to 0.

SED, [8]

SETEND instruction disable. Disables SETEND instructions at PL0 and PL1:

0SETEND instruction execution is enabled at PL0 and PL1.
1SETEND instructions are undefined at PL0 and PL1.

This field resets to 0.

ITD, [7]
res0All IT instruction functionality is always implemented in PL0, PL1 and enabled at PL2.
UNK, [6]

Writes to this bit are ignored. Reads of this bit return an UNKNOWN value.

CP15BEN, [5]

System instruction memory barrier enable. Enables accesses to the DMB, DSB, and ISB System instructions in the (coproc==1111) encoding space from PL1 and PL0.

0PL0 and PL1 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is UNDEFINED.
1PL0 and PL1 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is enabled.

This field resets to 1.

LSMAOE, [4]
Load/Store Multiple Atomicity and Ordering Enable.
res1This bit is not controllable. The ordering and interrupt behavior of Load/Store Multiple is as defined for Arm®v8‑A.
nTLSMD, [3]
no Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory.
res1

This bit is not controllable. Load/Store Multiple to memory marked at stage1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory does not generate a stage 1 alignment fault as a result of this mechanism.

C, [2]

Cacheability control, for data accesses at EL1 and EL0.

This field resets to 0.

A, [1]

Alignment check enable.

This field resets to 0.

M, [0]

MMU enable for EL1 and EL0 stage 1 address translation.

This field resets to 0.

Configurations

SCTLR (NS) is architecturally mapped to AArch64 register SCTLR_EL1. See B2.94 SCTLR_EL1, System Control Register, EL1.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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