B1.82 SDCR, Secure Debug Control Register

The SDCR Controls debug and performance monitors functionality in Secure state.

Bit field descriptions

SDCR is a 32-bit register, and is part of:

  • The Debug registers functional group.
  • The Security registers functional group.
Figure B1-71 SDCR bit assignments
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EPMAD, [21]

External debugger access to Performance Monitors registers disabled. This disables access to these registers by an external debugger:

0b0Access to Performance Monitors registers from external debugger is permitted. This is the reset value.
0b1Access to Performance Monitors registers from external debugger is disabled, unless overridden by authentication interface.
EDAD, [20]

External debugger access to breakpoint and watchpoint registers disabled. This disables access to these registers by an external debugger:

0b0Access to breakpoint and watchpoint registers from external debugger is permitted. This is the reset value.
0b1Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface.
SPME, [17]

Secure performance monitors enable. This allows event counting in Secure state:

0b0Event counting prohibited in Secure state. This is the reset value.
0b1Event counting allowed in Secure state.
SPD, [15:14]

AArch32 Secure privileged debug. Enables or disables debug exceptions from Secure state, other than Breakpoint Instruction exceptions. Valid values for this field are:

0b00

Legacy mode. Debug exceptions from Secure EL1 are enabled by the authentication interface. This is the reset value.

0b10

Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.

0b11

Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

Configurations

SDCR is mapped to AArch64 register MDCR_EL3. See B2.88 MDCR_EL3, Monitor Debug Configuration Register, EL3.

The SDCR is only accessible in Secure state.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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