B1.83 TTBCR, Translation Table Base Control Register

The TTBCR determines which of the translation table base registers defines the base address for a translation table walk required for the stage 1 translation of a memory access from any mode other than Hyp mode.

Also controls the translation table format and, when using the Long-descriptor translation table format, holds cacheability and shareability information.

Bit field descriptions

TTBCR is a 32-bit register, and is part of the Virtual memory control registers functional group.

There are two formats for this register. TTBCR.EAE determines which format of the register is used.


TTBCR (NS) is architecturally mapped to AArch64 register TCR_EL1[31:0]. See B2.97 TCR_EL1, Translation Control Register, EL1.

TTBCR (S) is architecturally mapped to AArch64 register TCR_EL3[31:0]. See B2.99 TCR_EL3, Translation Control Register, EL3.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
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