B1.83.2 TTBCR with Long-descriptor translation table format

TTBCR has a specific format when using the Long-descriptor translation table format. TTBCR.EAE determines which format of the register is in use.

The following figure shows the TTBCR bit assignments when TTBCR.EAE is 1.

Figure B1-73 TTBCR bit assignments, TTBCR.EAE is 1
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EAE, [31]

Extended Address Enable:

0b1Use the VMSAv8-32 translation system, with the Long-descriptor translation table format.
RES0, [30]
res0Reserved.
SH1, [29:28]

Shareability attribute for memory associated with translation table walks using TTBR1:

0b00Non-shareable.
0b10Outer Shareable.
0b11Inner Shareable.

Other values are reserved.

Resets to 0.

ORGN1, [27:26]

Outer cacheability attribute for memory associated with translation table walks using TTBR1:

0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.

Resets to 0.

IRGN1, [25:24]

Inner cacheability attribute for memory associated with translation table walks using TTBR1:

0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.

Resets to 0.

EPD1, [23]

Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1:

0b0Perform translation table walks using TTBR1.
0b1A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed.
A1, [22]

Selects whether TTBR0 or TTBR1 defines the ASID:

0b0TTBR0.ASID defines the ASID.
0b1TTBR1.ASID defines the ASID.
RES0, [21:19]
res0Reserved.
T1SZ, [18:16]

The size offset of the memory region addressed by TTBR1. The region size is 232-T1SZ bytes.

Resets to 0.

RES0, [15:14]
res0Reserved.
SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0:

0b00Non-shareable.
0b10Outer Shareable.
0b11Inner Shareable.

Other values are reserved.

Resets to 0.

ORGN0, [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0:

0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.

Resets to 0.

IRGN0, [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0:

0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.

Resets to 0.

EPD0, [7]

Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0:

0b0Perform translation table walks using TTBR0.
0b1A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed.
RES0, [6:3]
res0Reserved.
T0SZ, [2:0]

The size offset of the memory region addressed by TTBR0. The region size is 232-T0SZ bytes.

Resets to 0.

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