B1.85 TTBR0, Translation Table Base Register 0

The TTBR0 holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses from modes other than Hyp mode.

Usage constraints

TTBR0 is part of the Virtual memory control registers functional group.

There are two formats for this register. TTBCR.EAE determines which format of the register is used.


TTBR0 (NS) is architecturally mapped to AArch64 register TTBR0_EL1. See B2.100 TTBR0_EL1, Translation Table Base Register 0, EL1.

TTBR0 (S) is mapped to AArch64 register TTBR0_EL3. See B2.102 TTBR0_EL3, Translation Table Base Register 0, EL3.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.


TTBR0 is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, accesses read and write bits [31:0] and do not modify bits [63:32].

TTBCR.EAE determines which TTBR0 format is used:

  • EAE==0:

    32-bit format is used. TTBR0[63:32] are ignored.

  • EAE==1:

    64-bit format is used.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
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