B1.91 VTCR, Virtualization Translation Control Register

The VTCR controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure modes other than Hyp mode.

It also holds cacheability and shareability information for the accesses.

Bit field descriptions

VTCR is a 32-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Virtual memory control registers functional group.
Figure B1-80 VTCR bit assignments
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RES1, [31]
res1Reserved.
RES0, [30:14]
res0Reserved.
SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0.

0b00Non-shareable.
0b01Reserved.
0b10Outer Shareable.
0b11Inner Shareable.
ORGN0, [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0.

0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0.

0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
SL0, [7:6]

Starting level for translation table walks using VTTBR:

0b00Start at second level.
0b01Start at first level.
RES0, [5]
res0Reserved.
S, [4]
Sign extension bit. This bit must be programmed to the value of T0SZ[3]. If it is not, then the stage 2 T0SZ value is treated as an unknown value within the legal range that can be programmed.
T0SZ, [3:0]

The size offset of the memory region addressed by TTBR0. The region size is 232-T0SZ bytes.

Configurations

VTCR is architecturally mapped to AArch64 register VTCR_EL2. See B2.109 VTCR_EL2, Virtualization Translation Control Register, EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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