|Home > Register Descriptions > AArch32 system registers > VTCR, Virtualization Translation Control Register|
The VTCR controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure modes other than Hyp mode.
It also holds cacheability and shareability information for the accesses.
VTCR is a 32-bit register, and is part of:
Shareability attribute for memory associated with translation table walks using TTBR0.
Outer cacheability attribute for memory associated with translation table walks using TTBR0.
|Normal memory, Outer Non-cacheable.|
|Normal memory, Outer Write-Back Write-Allocate Cacheable.|
|Normal memory, Outer Write-Through Cacheable.|
|Normal memory, Outer Write-Back no Write-Allocate Cacheable.|
Inner cacheability attribute for memory associated with translation table walks using TTBR0.
|Normal memory, Inner Non-cacheable.|
|Normal memory, Inner Write-Back Write-Allocate Cacheable.|
|Normal memory, Inner Write-Through Cacheable.|
|Normal memory, Inner Write-Back no Write-Allocate Cacheable.|
Starting level for translation table walks using VTTBR:
|Start at second level.|
|Start at first level.|
The size offset of the memory region addressed by TTBR0. The region size is 232-T0SZ bytes.
VTCR is architecturally mapped to AArch64 register VTCR_EL2. See B2.109 VTCR_EL2, Virtualization Translation Control Register, EL2.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.