B2.6 ACTLR_EL2, Auxiliary Control Register, EL2

The ACTLR_EL2 provides IMPLEMENTATION DEFINED configuration and control options for EL2.

Bit field descriptions

ACTLR_EL2 is a 64-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Other system control registers functional group.
  • The IMPLEMENTATION DEFINED functional group.
Figure B2-2 ACTLR_EL2 bit assignments
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RES0, [63:13]
RES0 Reserved.
CLUSTERPMUEN, [12]

Performance Management Registers enable. The possible values are:

0CLUSTERPM* registers are not write-accessible from a lower Exception level. This is the reset value.
1CLUSTERPM* registers are write-accessible from EL1 Non-secure if they are write-accessible from EL2.
SMEN, [11]

Scheme Management Registers enable. The possible values are:

0Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR, CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are not write-accessible from EL1 Non-secure. This is the reset value.
1Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR, CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are write-accessible from EL1 Non-secure if they are write-accessible from EL2.
TSIDEN, [10]

Thread Scheme ID Register enable. The possible values are:

0Register CLUSTERTHREADSID is not write-accessible from EL1 Non-secure. This is the reset value.
1Register CLUSTERTHREADSID is write-accessible from EL1 Non-secure if they are write-accessible from EL2.
RES0, [9:8]
RES0Reserved.
PWREN, [7]

Power Control Registers enable. The possible values are:

0Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN, CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are not write-accessible from EL1 Non-secure. This is the reset value.
1Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN, CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are write-accessible from EL1 Non-secure if they are write-accessible from EL2.
RES0, [6]
RES0Reserved.
ERXPFGEN, [5]

Error Record Registers enable. The possible values are:

0ERXPFG* are not write-accessible from EL1 Non-secure. This is the reset value.
1ERXPFG* are write-accessible from EL1 Non-secure if they are write-accessible from EL2.
RES0, [4:2]
RES0Reserved.
ECTLREN, [1]

Extended Control Registers enable. The possible values are:

0CPUECTLR and CLUSTERECTLR are not write-accessible from EL1 Non-secure. This is the reset value.
1CPUECTLR and CLUSTERECTLR are write-accessible from EL1 Non-secure if they are write-accessible from EL2.
ACTLREN, [0]

Auxiliary Control Registers enable. The possible values are:

0CPUACTLR and CLUSTERACTLR are not write-accessible from EL1 Non-secure. This is the reset value.
1CPUACTLR and CLUSTERACTLR are write-accessible from EL1 Non-secure if they are write-accessible from EL2.
Configurations

ACTLR_EL2 bits [31:0] are architecturally mapped to the AArch32 HACTLR register. See B1.48 HACTLR, Hyp Auxiliary Control Register.

ACTLR_EL2 bits [63:32] are architecturally mapped to the AArch32 HACTLR2 register. See B1.49 HACTLR2, Hyp Auxiliary Control Register 2.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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