B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1

AFSR1_EL1 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are taken to EL1. This register is not used in Cortex®-A55.

Bit field descriptions

AFSR1_EL1 is a 32-bit register, and is part of:

  • The Exception and fault handling registers functional group.
  • The IMPLEMENTATION DEFINED functional group.
Figure B2-7 AFSR1_EL1 bit assignments
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RES0, [31:0]
Reserved, RES0.

AFSR1_EL1 is architecturally mapped to AArch32 register AIFSR. See B1.10 AIFSR, Auxiliary Instruction Fault Status Register.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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