B2.24 CLIDR_EL1, Cache Level ID Register, EL1

The CLIDR_EL1 identifies the type of cache, or caches, implemented at each level, up to a maximum of seven levels.

It also identifies the Level of Coherency (LoC) and Level of Unification (LoU) for the cache hierarchy.

Bit field descriptions

CLIDR_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-19 CLIDR_EL1 bit assignments
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RES0, [63:33]
res0 Reserved.
ICB, [32:30]

Inner cache boundary. This field indicates the boundary between the inner and the outer domain:

001 L1 cache is the highest inner level.
010 L2 cache is the highest inner level.
011 L3 cache is the highest inner level.
LoUU, [29:27]

Indicates the Level of Unification Uniprocessor for the cache hierarchy:

000 No levels of cache need to cleaned or invalidated when cleaning or invalidating to the Point of Unification. This is the value if no cache are configured.
LoC, [26:24]

Indicates the Level of Coherency for the cache hierarchy:

001 L2 and L3 cache are not implemented.
010 L2 or L3 cache is not implemented.
011 L2 and L3 cache are implemented.
LoUIS, [23:21]

Indicates the Level of Unification Inner Shareable (LoUIS) for the cache hierarchy.

0b000No levels of cache need to be cleaned or invalidated when cleaning or invalidating to the Point of Unification.
RES0, [20:9]

No cache at levels L7 down to L4.

res0 Reserved.
Ctype3, [8:6]

Indicates the type of cache if the cluster implements L3 cache. If present, unified instruction and data caches at Level-3:

000 L2 or L3 cache is not implemented.
100 L2 and L3 cache are implemented.

If Ctype2 has a value of 3b000, the value of Ctype3 must be ignored.

Ctype2, [5:3]

Indicates the type of cache if the core implements L2 cache. If present, unified instruction and data caches at Level-2:

000 L2 and L3 cache are not implemented.
100 L2 or L3 cache is implemented as a unified cache.
Ctype1, [2:0]

Indicates the type of cache implemented at L1:

011 Separate instruction and data caches at L1.
Configurations

CLIDR_EL1 is architecturally mapped to AArch32 register CLIDR. See B1.16 CLIDR, Cache Level ID Register.

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