B2.25 CPACR_EL1, Architectural Feature Access Control Register, EL1

The CPACR_EL1 controls access to Advanced SIMD and floating-point functionality from EL0, EL1, and EL3.

Bit field descriptions

CPACR_EL1 is a 32-bit register, and is part of the Other system control registers functional group.

Figure B2-20 CPACR_EL1 bit assignments
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RES0, [31:22]
res0 Reserved.
FPEN, [21:20]

Traps instructions that access registers associated with Advanced SIMD and floating-point execution to trap to EL1 when executed from EL0 or EL1. The possible values are:

0b00 Trap any instruction in EL0 or EL1 that uses registers associated with Advanced SIMD and floating-point execution. The reset value is 0b00.
0b01 Trap any instruction in EL0 that uses registers associated with Advanced SIMD and floating-point execution. Instructions in EL1 are not trapped.
0b10 Trap any instruction in EL0 or EL1 that uses registers associated with Advanced SIMD and floating-point execution.
0b11 No instructions are trapped.

This field is res0 if Advanced SIMD and floating-point are not implemented.

RES0, [19:0]
res0 Reserved.
Configurations

CPACR_EL1 is architecturally mapped to AArch32 register CPACR. See B1.17 CPACR, Architectural Feature Access Control Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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