B2.27 CPTR_EL3, Architectural Feature Trap Register, EL3

The CPTR_EL3 controls trapping to EL3 of access to CPACR_EL1, CPTR_EL2, trace functionality and registers associated with Advanced SIMD and floating-point execution.

It also controls EL3 access to trace functionality and registers associated with Advanced SIMD and floating-point execution.

Bit field descriptions

CPTR_EL3 is a 32-bit register, and is part of the Security registers functional group.

Figure B2-22 CPTR_EL3 bit assignments
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TTA, [20]

Trap Trace Access.

Not implemented. RES0.

TFP, [10]

This causes instructions that access the registers that are associated with Advanced SIMD or floating-point execution to trap to EL3 when executed from any Exception level, unless trapped to EL1 or EL2. The possible values are: are:

0

Does not cause any instruction to be trapped. This is the reset value if the Advanced SIMD and floating-point support is implemented.

1

Causes any instructions that use the registers that are associated with Advanced SIMD or floating-point execution to be trapped. This is always the value if the Advanced SIMD and floating-point support is not implemented.

Configurations

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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