B2.51 ESR_EL1, Exception Syndrome Register, EL1

The ESR_EL1 holds syndrome information for an exception taken to EL1.

Bit field descriptions

ESR_EL1 is a 32-bit register, and is part of the Exception and fault handling registers functional group.

Figure B2-37 ESR_EL1 bit assignments
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EC, [31:26]
Exception Class. Indicates the reason for the exception that this register holds information about.
IL, [25]

Instruction Length for synchronous exceptions. The possible values are:

0 16-bit.
1 32-bit.

This field is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack pointer misalignment, Data Aborts for which the ISV bit is 0, exceptions caused by an illegal instruction set state, and exceptions using the 0x00 Exception Class.

ISS Valid, [24]

Syndrome valid. The possible values are:

0 ISS not valid, ISS is res0.
1 ISS valid.
ISS, [23:0]

Syndrome information.

When the EC field is 0x2F, indicating an SError interrupt has occurred, the ISS field contents are IMPLEMENTATION DEFINED.

Configurations

ESR_EL1 is architecturally mapped to AArch32 register DFSR (NS). See B1.28 DFSR, Data Fault Status Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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