B2.54 HACR_EL2, Hyp Auxiliary Configuration Register, EL2

HACR_EL2 controls trapping to EL2 of IMPLEMENTATION DEFINED aspects of Non-secure EL1 or EL0 operation. This register is not used in the Cortex®-A55 core.

Bit field descriptions

HACR_EL2 is a 32-bit register, and is part of Virtualization registers functional group.

Figure B2-40 HACR_EL2 bit assignments
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RES0, [31:0]
Reserved, RES0.

AArch64 System register HACR_EL2 is architecturally mapped to AArch32 System register HACR. See B1.47 HACR, Hyp Auxiliary Configuration Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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