B2.55 HCR_EL2, Hypervisor Configuration Register, EL2

The HCR_EL2 provides configuration control for virtualization, including whether various Non-secure operations are trapped to EL2.

Bit field descriptions

HCR_EL2 is a 64-bit register, and is part of the Virtualization registers functional group.

Figure B2-41 HCR_EL2 bit assignments
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RES0, [63:39]
res0 Reserved.
MIOCNCE, [38]

Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1 and EL0 translation regime.

This bit is not implemented, RAZ/WI.

RW, [31]

Execution state control for lower Exception levels. The possible values are:

0Lower levels are all AArch32.
1The Execution state for EL1 is AArch64. The Execution state for EL0 is determined by the current value of PSTATE.nRW when executing at EL0.
HCD, [29]

HVC instruction disable.

This bit is reserved, res0.
TGE, [27]

Traps general exceptions. If this bit is set, and SCR_EL3.NS is set, then:

  • All exceptions that would be routed to EL1 are routed to EL2.
  • The SCTLR_EL1.M bit is treated as 0 regardless of its actual state, other than for reading the bit.
  • The HCR_EL2.FMO, IMO, and AMO bits are treated as 1 regardless of their actual state, other than for reading the bits.
  • All virtual interrupts are disabled.
  • Any IMPLEMENTATION DEFINED mechanisms for signaling virtual interrupts are disabled.
  • An exception return to EL1 is treated as an illegal exception return.

HCR_EL2.TGE must not be cached in a TLB.

When the value of SCR_EL3.NS is 0 the core behaves as if this field is 0 for all purposes other than a direct read or write access of HCR_EL2.

TID3, [18]

Traps ID group 3 registers. The possible values are:

0 ID group 3 register accesses are not trapped.
1 Reads to ID group 3 registers executed from Non-secure EL1 are trapped to EL2.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for the registers covered by this setting.

TID0, [15]

Trap ID Group 0. When 1, this causes reads to the following registers executed from EL1 or EL0 if not undefined to be trapped to EL2:

FPSID and JIDR.

When the value of SCR_EL3.NS is 0 the PE behaves as if this field is 0 for all purposes other than a direct read or write access of HCR_EL2.

SWIO, [1]

Set/Way Invalidation Override. Non-secure EL1 execution of the data cache invalidate by set/way instruction is treated as data cache clean and invalidate by set/way.

This bit is res1.

Configurations

HCR_EL2[31:0] is architecturally mapped to AArch32 register HCR. See B1.54 HCR, Hyp Configuration Register.

HCR_EL2[63:32] is architecturally mapped to AArch32 register HCR2. See B1.55 HCR2, Hyp Configuration Register 2.

If EL2 is not implemented, this register is RES0 from EL3

RW fields in this register reset to architecturally UNKNOWN values.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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