B2.56 HPFAR_EL2, Hypervisor IPA Fault Address Register, EL2

The HPFAR_EL2 holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.

Bit field descriptions

HPFAR_EL2 is a 64-bit register, and is part of:

  • The Exception and fault handling registers functional group.
  • The Virtualization registers functional group.
Figure B2-42 HPFAR_EL2 bit assignments
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RES0, [63:40]
res0 Reserved.
FIPA[47:12], [39:4]

Bits [47:12] of the faulting intermediate physical address. The equivalent upper bits in this field are res0.

RES0, [3:0]
res0 Reserved.
Configurations

AArch64 register HPFAR_EL2[31:0] is architecturally mapped to AArch32 register HPFAR. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

If EL2 is not implemented, this register is res0 from EL3.

RW fields in this register reset to architecturally unknown values.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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