B2.67 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1

The ID_ISAR0_EL1 provides information about the instruction sets implemented by the core in AArch32.

Bit field descriptions

ID_ISAR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-53 ID_ISAR0_EL1 bit assignments
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RES0, [31:28]
RES0 Reserved.
Divide, [27:24]

Indicates the implemented Divide instructions:

  • SDIV and UDIV in the T32 instruction set.
  • SDIV and UDIV in the A32 instruction set.
Debug, [23:20]

Indicates the implemented Debug instructions:

0x1 BKPT.
Coproc, [19:16]

Indicates the implemented Coprocessor instructions:

0x0 None implemented, except for instructions separately attributed by the architecture to provide access to AArch32 System registers and System instructions.
CmpBranch, [15:12]

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:

0x1 CBNZ and CBZ.
Bitfield, [11:8]

Indicates the implemented bit field instructions:

0x1 BFC, BFI, SBFX, and UBFX.
BitCount, [7:4]

Indicates the implemented Bit Counting instructions:

0x1 CLZ.
Swap, [3:0]

Indicates the implemented Swap instructions in the A32 instruction set:

0x0 None implemented.

ID_ISAR0_EL1 is architecturally mapped to AArch32 register ID_ISAR0. See B1.61 ID_ISAR0, Instruction Set Attribute Register 0.

In an AArch64-only implementation, this register is UNKNOWN.

Must be interpreted with ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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