B2.68 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1

The ID_ISAR1_EL1 provides information about the instruction sets implemented by the core in AArch32.

Bit field descriptions

ID_ISAR1_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-54 ID_ISAR1_EL1 bit assignments
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Jazelle, [31:28]

Indicates the implemented Jazelle state instructions:

0x1 Adds the BXJ instruction, and the J bit in the PSR.
Interwork, [27:24]

Indicates the implemented Interworking instructions:

  • The BX instruction, and the T bit in the PSR.
  • The BLX instruction. The PC loads have BX-like behavior.
  • Data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear, have BX-like behavior.
Immediate, [23:20]

Indicates the implemented data-processing instructions with long immediates:

  • The MOVT instruction.
  • The MOV instruction encodings with zero-extended 16-bit immediates.
  • The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates, and other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for those encodings.
IfThen, [19:16]

Indicates the implemented If-Then instructions in the T32 instruction set:

0x1 The IT instructions, and the IT bits in the PSRs.
Extend, [15:12]

Indicates the implemented Extend instructions:

  • The SXTB, SXTH, UXTB, and UXTH instructions.
  • The SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions.
Except_AR, [11:8]

Indicates the implemented A profile exception-handling instructions:

0x1 The SRS and RFE instructions, and the A profile forms of the CPS instruction.
Except, [7:4]

Indicates the implemented exception-handling instructions in the A32 instruction set:

0x1 The LDM (exception return), LDM (user registers), and STM (user registers) instruction versions.
Endian, [3:0]

Indicates the implemented Endian instructions:

0x1 The SETEND instruction, and the E bit in the PSRs.

ID_ISAR1_EL1 is architecturally mapped to AArch32 register ID_ISAR1. See B1.62 ID_ISAR1, Instruction Set Attribute Register 1.

In an AArch64-only implementation, this register is unknown.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1 and ID_ISAR5_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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