B2.71 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1

The ID_ISAR4_EL1 provides information about the instruction sets implemented by the core in AArch32.

Bit field descriptions

ID_ISAR4_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-57 ID_ISAR4_EL1 bit assignments
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SWP_frac, [31:28]

Indicates support for the memory system locking the bus for SWP or SWPB instructions:

0x0 SWP and SWPB instructions not implemented.
PSR_M, [27:24]

Indicates the implemented M profile instructions to modify the PSRs:

0x0 None implemented.
SynchPrim_frac, [23:20]

This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization Primitive instructions:

  • The LDREX and STREX instructions.
  • The CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.
  • The LDREXD and STREXD instructions.
Barrier, [19:16]

Indicates the supported Barrier instructions in the A32 and T32 instruction sets:

0x1 The DMB, DSB, and ISB barrier instructions.
SMC, [15:12]

Indicates the implemented SMC instructions:

0x1 The SMC instruction.
WriteBack, [11:8]

Indicates the support for Write-Back addressing modes:

0x1 Core supports all the Write-Back addressing modes as defined in Arm®v8‑A.
WithShifts, [7:4]

Indicates the support for instructions with shifts.

  • Support for shifts of loads and stores over the range LSL 0-3.
  • Support for other constant shift options, both on load/store and other instructions.
  • Support for register-controlled shift options.
Unpriv, [3:0]

Indicates the implemented unprivileged instructions.

  • The LDRBT, LDRT, STRBT, and STRT instructions.
  • The LDRHT, LDRSBT, LDRSHT, and STRHT instructions.

ID_ISAR4_EL1 is architecturally mapped to AArch32 register ID_ISAR4. See B1.65 ID_ISAR4, Instruction Set Attribute Register 4.

In an AArch64-only implementation, this register is UNKNOWN.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, and ID_ISAR5_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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