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The ID_PFR1_EL1 provides information about the programmers model and architecture extensions supported by the core.
ID_PFR1_EL1 is a 32-bit register, and must be interpreted with ID_PFR0. It is part of the Identification registers functional group.
This register is Read Only.
GIC CPU support:
||GIC CPU interface is disabled, GICCDISABLE is HIGH.|
||GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.|
Generic Timer support:
||Generic Timer is implemented.|
Indicates support for Virtualization:
||The following Virtualization is implemented:
M profile programmers model support:
||The following Security items are implemented:
Indicates support for the standard programmers model for Armv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes:
ID_PFR1_EL1 is architecturally mapped to AArch32 register ID_PFR1. See B1.74 ID_PFR1, Processor Feature Register 1.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.