B2.82 IFSR32_EL2, Instruction Fault Status Register, EL2

The IFSR32_EL2 allows access to the AArch32 IFSR register from AArch64 state only. Its value has no effect on execution in AArch64 state.

Bit field descriptions

IFSR32_EL2 is a 32-bit register, and is part of the Exception and fault handling registers functional group.

There are two formats for this register. The current translation table format determines which format of the register is used.

Configurations

IFSR32_EL2 is architecturally mapped to AArch32 register IFSR(NS). See B1.75 IFSR, Instruction Fault Status Register.

RW fields in this register reset to unknown values.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.