B2.88 MDCR_EL3, Monitor Debug Configuration Register, EL3

The MDCR_EL3 provides configuration options for Security to self-hosted debug.

Bit field descriptions

MDCR_EL3 is a 32-bit register, and is part of:

  • The Debug registers functional group.
  • The Security registers functional group.
Figure B2-75 MDCR_EL3 bit assignments
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EPMAD, [21]

External debugger access to Performance Monitors registers disabled. This disables access to these registers by an external debugger. The possible values are:

0 Access to Performance Monitors registers from external debugger is permitted.
1 Access to Performance Monitors registers from external debugger is disabled, unless overridden by authentication interface.
EDAD, [20]

External debugger access to breakpoint and watchpoint registers disabled. This disables access to these registers by an external debugger. The possible values are:

0 Access to breakpoint and watchpoint registers from external debugger is permitted.
1 Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface.
SPME, [17]

Secure performance monitors enable. This enables event counting exceptions from Secure state. The possible values are:

0 Event counting prohibited in Secure state.
1 Event counting allowed in Secure state.
SPD32, [15:14]

AArch32 secure privileged debug. Enables or disables debug exceptions from Secure state if Secure EL1 is using AArch32, other than software breakpoint instructions. The possible values are:

00 Legacy mode. Debug exceptions from Secure EL1 are enabled only if AArch32SelfHostedSecurePrivilegedInvasiveDebugEnabled().
01 Reserved.
10 Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.
11 Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

The reset value is UNKNOWN.

TDOSA, [10]

Trap accesses to the OS debug system registers, OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, and DBGPRCR_EL1 OS.

0 Accesses are not trapped.
1 Accesses to the OS debug system registers are trapped to EL3.

The reset value is UNKNOWN.

TDA, [9]

Trap accesses to the remaining sets of debug registers to EL3.

0 Accesses are not trapped.
1 Accesses to the remaining debug system registers are trapped to EL3.

The reset value is UNKNOWN.

Configurations

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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