B2.94 SCTLR_EL1, System Control Register, EL1

The SCTLR_EL1 provides top level control of the system, including its memory system, at EL1 and EL0.

Bit field descriptions

SCTLR_EL1 is a 32-bit register, and is part of the Other system control registers functional group.

Figure B2-81 SCTLR_EL1 bit assignments
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EE, [25]

Exception endianness. The value of this bit controls the endianness for explicit data accesses at EL1. This value also indicates the endianness of the translation table data for translation table lookups. The possible values of this bit are:

0 Little-endian.
1 Big-endian.

The reset value of this bit is determined by the CFGEND configuration signal.

E0E, [24]

Endianness of explicit data access at EL0. The possible values are:

0 Explicit data accesses at EL0 are little-endian. This is reset value.
1 Explicit data accesses at EL0 are big-endian.
SED, [8]

SETEND instruction disable. The possible values are:

0 The SETEND instruction is enabled. This is the reset value.
1 The SETEND instruction is undefined.

SCTLR_EL1 is architecturally mapped to AArch32 register SCTLR(NS) See B1.81 SCTLR, System Control Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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