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The SCTLR_EL2 provides top-level control of the system, including its memory system at EL2.
SCTLR_EL2 is a 32-bit register, and is part of:
Apart from bits , , and , this register resets to unknown values.
SCTLR_EL2 is architecturally mapped to AArch32 register HSCTLR. See B1.56 HSCTLR, Hyp System Control Register.
If EL2 is not implemented, this register is RES0 from EL3.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.