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The SCTLR_EL3 provides top level control of the system, including its memory system at EL3.
SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.
Exception endianness. This bit controls the endianness for:
The possible values are:
|Little endian. This is the reset value.|
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL3 using AArch64. Otherwise, RW fields in this register reset to architecturally unknown values.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.