B2.96 SCTLR_EL3, System Control Register, EL3

The SCTLR_EL3 provides top level control of the system, including its memory system at EL3.

Bit field descriptions

SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.

Figure B2-83 SCTLR_EL3 bit assignments
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EE, [25]

Exception endianness. This bit controls the endianness for:

  • Explicit data accesses at EL3.
  • Stage 1 translation table walks at EL3.

The possible values are:

0Little endian. This is the reset value.
1Big endian.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL3 using AArch64. Otherwise, RW fields in this register reset to architecturally unknown values.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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