B2.98 TCR_EL2, Translation Control Register, EL2

The TCR_EL2 controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.

Bit field descriptions

TCR_EL2 is a 64-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Virtual memory control registers functional group.

The register has configurations of bit assignment dependent upon whether the core is running a hypervisor or running a host Host Operating System. This is controlled by the value of the E2H bit in register HCR_EL2:

0Hpervisor configuration, see When HCR_EL2.E2H==0.
1Host Operating System configuration: HCR_EL2.E2H==1 Address translation aborted, see When HCR_EL2.E2H==1.
Configurations

TCR_EL2 is architecturally mapped to AArch32 register HTCR. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

If EL2 is not implemented, this register is res0 from EL3.

RW fields in this register reset to architecturally unknown values.

When HCR_EL2.E2H==0

Figure B2-85 TCR_EL2 bit assignments when HCR_EL2.E2H==0
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HPD, [24]

Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL2. The possible values are:

0Hierarchical Permissions are enabled.
1Hierarchical Permissions are disabled.

Note:

In this case bit[61] (APTable[0]) and bit[59] (PXNTable) of the next level descriptor attributes are required to be to be ignored by the PE, and are no longer reserved, allowing them to be used by software.
HD, [22]

Hardware management of dirty state in stage 1 translations from EL2. The possible values are:

0Stage 1 hardware management of dirty state disabled.
1Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.

Implementation of this bit is OPTIONAL, and, if not implemented, this bit is res0.

HA, [21]

Hardware Access flag update in stage 1 translations from EL2. The possible values are:

0Stage 1 Access flag update disabled.
1Stage 1 Access flag update enabled.
PS, [18:16]

Physical address size. The possible values are:

0b00032 bits, 4GB.
0b00136 bits, 64GB.
0b01040 bits, 1TB.

Other values are reserved.

TG0, [15:14]

TTBR0_EL2 granule size. The possible values are:

0b004KB.
0b0164KB.
0b1016KB.
0b11Reserved.

All other values are not supported.

SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0_EL2.

The possible values are:

0b00Non-shareable.
0b01Reserved.
0b10Outer shareable.
0b11Inner shareable.

When HCR_EL2.E2H==1

Figure B2-86 TCR_EL2 bit assignments when HCR_EL2.E2H==1
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HD, [40]

Hardware management of dirty state in stage 1 translations from EL0 and EL1. The possible values are:

0Stage 1 hardware management of dirty state disabled.
1Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.

Implementation of this bit is OPTIONAL, and, if not implemented, this bit is res0.

HA, [39]

Hardware Access flag update in stage 1 translations from EL0 and EL1. The possible values are:

0Stage 1 Access flag update disabled.
1Stage 1 Access flag update enabled.

Implementation of this bit is OPTIONAL, and, if not implemented, this bit is res0.

TG0, [15:14]

TTBR0_EL1 granule size. The possible values are:

0b004KB.
0b1016KB.
0b0164KB.
0b11Reserved.

All other values are not supported.

SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0_EL1. The possible values are:

0b00Non-shareable.
0b01Reserved.
0b10Outer shareable.
0b11Inner shareable.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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