B2.99 TCR_EL3, Translation Control Register, EL3

The TCR_EL3 controls translation table walks required for stage 1 translation of memory accesses from EL3 and holds cacheability and shareability information for the accesses.

Bit field descriptions

TCR_EL3 is a 32-bit register, and is part of the Virtual memory control registers functional group.

Figure B2-87 TCR_EL3 bit assignments
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HPD, [24]

Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL3. The possible values are:

0Hierarchical Permissions are enabled.
1Hierarchical Permissions are disabled.


In this case bit[61] (APTable[0]) and bit[59] (PXNTable) of the next level descriptor attributes are required to be to be ignored by the PE, and are no longer reserved, allowing them to be used by software.
HD, [22]

Hardware management of dirty state in stage 1 translations from EL3. The possible values are:

0Stage 1 hardware management of dirty state disabled.
1Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.

Implementation of this bit is OPTIONAL, and, if not implemented, this bit is res0.

HA, [21]

Hardware Access flag update in stage 1 translations from EL3. The possible values are:

0Stage 1 Access flag update disabled.
1Stage 1 Access flag update enabled.
PS, [18:16]

Physical address size. The possible values are:

0b00032 bits, 4GB.
0b00136 bits, 64GB.
0b01040 bits, 1TB.

Other values are reserved.

TG0, [15:14]

TTBR0_EL3 granule size. The possible values are:


All other values are not supported.

SH0, [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0_EL3.

The possible values are:

0b10Outer shareable.
0b11Inner shareable.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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