B2.100 TTBR0_EL1, Translation Table Base Register 0, EL1

The TTBR0_EL1 holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses from modes other than Hyp mode.

This register is used when HCR_EL2.E2H is 0.


When HCR_EL2.E2H is 1, TTBR0_EL2 is used.

Bit field descriptions

TTBR0_EL1 is a 64-bit register, and is part of the Virtual memory control registers functional group.

Figure B2-88 TTBR0_EL1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

ASID, [63:48]

An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID.

BADDR, [47:2]

Translation table base address.

RES0, [1]
CnP, [0]
Common not Private. Supports selective sharing of TLB entries across multiple cores. The value is:

CnP is not supported.


CnP is supported.

TTBR0_EL1 is architecturally mapped to AArch32 register TTBR0. See B1.85 TTBR0, Translation Table Base Register 0.

RW fields in this register reset to architecturally unknown values.

Any of the fields in this register are permitted to be cached in a TLB.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.