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The TTBR1_EL1 holds the base address of translation table 1, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses at EL0 and EL1.
This register is used when HCR_EL2.E2H is 0.
TTBR1_EL1 is a 64-bit register, and is part of the Virtual memory control registers functional group.
An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID.
Translation table base address.
CnP is not supported.
CnP is supported.
RW fields in this register reset to architecturally unknown values.
Any of the fields in this register are permitted to be cached in a TLB.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.